Many of today's commercial integrated circuit (IC) devices and multi-chip modules (MCM) cannot be utilized in deep space and earth orbiting applications because of total dose radiation induced damage. Commercial IC devices are developed and manufactured for computer and mass market applications and are not designed to withstand the effects of the natural space environment. The radiation effects include solar flares, galactic cosmic radiation and the Van Allen trapped electron and proton belts or man-made radiation induced events (neutrons and gamma radiation).
Typical commercial silicon integrated circuits fail to operate when exposed to total doses of two to fifteen kilorads(Si). Common methods used to prevent radiation degradation in performance are: 1) to design special radiation tolerant die, 2) to shield the entire component and board assembly, or 3) shield the individual component. There are weight, cost and time-to-market penalties depending on the method. For example, specially designed radiation tolerant die are time consuming and expensive to produce, since the part must be redesigned to incorporate radiation hardening techniques. Examples of such methods include U.S. Pat. Nos. 3,933,530; 4,014,772; 4,148,049; 4,313,7684; 4,402,002; 4,675,978; 4,825,278; 4,833,334; 4,903,108; 5,001,528; 5,006,479; 5,024,965; 5,140,390; 5,220,192; and 5,324,952, each of which patent is incorporated herein by reference. Reference may also be made to Japan patent 62-125651, Jun. 6, 1987, and articles entitled "Effects of Material and/or Structure on Shielding of Electronic Devices," R. Mangeret, T. Carriere, J. Beacour, T. M. Jordan, IEEE 1996; and "Novice, a Radiation Transport/Shielding Code", T. M. Jordan, E. M. P. Consultants Report, January 1960, the Japan patent and such articles being incorporated herein by reference.
Such techniques delay the time to market the products. As a result, these conventional radiation hardened devices are usually two to three generations behind the current commercial technological advances in both size and capabilities. There are additional penalties in limited marketability and demand, and hence low volume productions of the die result. Consequently, such methods produce a more expensive product, which is technologically behind the commercially available microelectronics, with slower speed and less capability. Additionally, because of the limited market for these products, they are frequently not available at all.
Such radiation shielding methods involve using metal shielding external to the package. Shielding by other mechanical or electrical elements complicates the platform design, often requiring complex three dimensional modeling of the design.
Another attempt at shielding includes disposing a small shield on the surface of the package. Such a technique does not provide effective three-dimensional shielding protection. Additionally, the small external shield is generally thermally mismatched to the package, and increases the size and weight of the package.
Examples of system level shielding are disclosed in U.S. Pat. Nos. 4,833,334 and 5,324,952, which are incorporated by reference as if fully set forth herein. The U.S. Pat. No. 4,833,334 discloses the use of a protective box to house sensitive electronic components. The box is partially composed of a high atomic weight material to shield effectively against x-rays. However this approach has the serious disadvantage of adding substantial bulk and weight to electronic circuit assemblies protected in this manner. Moreover, it would be expensive to provide this type of protection to individual integrated circuits as manufacturing custom boxes for each circuit configuration would be costly.
The method of shielding material on the outside of the package is known as spot shielding. Such a technique is disclosed in Japanese patent publication 62-125651, published Jun. 6, 1987, which is incorporated by reference as if fully set forth herein. This patent describes a spot shielded semiconductor device which utilizes a double layered shield film to serve as a sealing cover on an upper surface of a semiconductor package. Another double layered shield film is attached to a lower surface of the package. However, space qualified microelectronic parts must be capable of withstanding the enormous forces exerted during acceleration periods during space travel. The external shields are subject to tearing or prying off from the sealing cover. The use of a double layer shield film only slightly reduces the weight of the package, but increases the size of the package unnecessarily. Also, thin films are generally only effective at shielding electromagnetic interference (EMI) radiation and are ineffective at shielding ionizing radiation found in space. Examples of this type of EMI or EMF shielding devices include devices disclosed in U.S. Pat. Nos. 4,266,239; 4,823,523; and 4,868,716, which are incorporated herein by reference.
The significant disadvantage of the spot shielding method includes an increase in weight and thickness of the device, and an increase in exposure of the semiconductor to side angle radiation due to the shielding being spaced apart from the semiconductor.
Many conventional microcircuits are only available in prepackaged form, or the die is already mounted onto the circuit board. Therefore, it would be highly desirable to have technique and shielding compositions for shielding parts already packaged or mounted on a circuit board, or in bare IC die form. Such compositions should be relatively inexpensive to manufacture and use, and are compact in size. In this regard, such new and improved techniques should be very convenient to employ in a highly effective manner, and yet be relatively inexpensive to manufacture.